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Enabling Technologies for Networks on Chip Special Issue

Editorial Board
Special Issue Editors:
  • Mithun Mukherjee (GUDP)

The growth in number of transistors with technology has propelled the integration of several processing elements onto a single silicon chip, a.k.a. System-on-Chip (SoC).To compensate for this fast-paced technological scalability with the performance bottleneck of conventional bus-based interconnect, Network-on-Chip (NoC) has emerged as an alternative on-chip communication platform that facilitates the integration of novel interconnect fabrics such as optical networks, three-dimensional integrated circuits (3D ICs), surface-wave and millimetre-wave (mm-wave) for emerging SoC design.

Several research efforts have been made to mitigate the performance and manufacturing cost in terms of silicon area, power consumption, reliability, latency and throughput of the NoC. However, merely metal-based interconnect stretches performance limits under the continuous and relentless technology scaling which calls for on-going investigation and development in this field. EAI Transactions on Industrial Networks and Intelligent Systems seeks original manuscripts for a special issue on “Enabling Technologies for Networks-on-Chip”, scheduled for publication in December 2018.

  • NoC interconnect (wireless NoC, photonics, quantum, etc)
  • Fault-tolerance and reliability of NoC• Off-chip networks
  • Application-specific design for NoC
  • Channel modelling for wireless NoC via mm-wave and THz bands• Modulation and coding for THz band communications in NoC
  • Information theoretic issues of THz band communications in NoC
  • Parallel programming and software models for wired/wireless NoC
  • Multicore architectures for three-dimensional NoC (3D NoC)
  • Integration and packaging of 3D NoC and heterogeneous NoC.
Manuscript submission deadline:
Notification of acceptance:
Submission of final revised paper:
Publication of special issue (tentative):
March 2019

Industrial Networks and Intelligent Systems